Large scale integration techniques have brought about the construction of large arrays of binary storage elements on a single chip of silicon. These storage cells, typically using MOS technology, consist of multi-component circuits in a conventional bistable configuration. There are numerous advantages of such semiconductor storage devices including high packing density and low power requirements of such memory cells.
With the advancement of semiconductor technology, there has been a need to increase the number of data bits stored per unit area on the semiconductor chip. The increased storage capacity decreases the cost of manufacture of a semiconductor memory. In the course of the evolution of the semiconductor industry, the technique of ion implantation into the channel region of a field-effect transistor device has been developed to adjust the threshold voltage for the device so that the gate voltage at which the device will switch can be customized. With the use of ion implantation, memory cells have been developed which utilize field-effect transistors having different threshold voltages for multi-bit data storage. These field-effect transistors require sensing circuitry for determining the threshold voltage for each memory cells. Multi-bit field-effect transistors and one such sensing scheme is described in U.S. Pat. No. 4,202,044 issued to Beilstein, Jr. et al on May 6, 1980 and entitled "Quaternary FET Read Only Memory".
A need has thus arisen for a multi-bit read only memory circuit for use with read only memory storage devices utilizing multi-level ion implantation to set multi-level threshold voltage levels in the storage devices. Such a circuit must be simple in construction, operate at maximum speed and complement the advantages of multi-bit read only memory cells.